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マインドマップギャラリー digital logic circuit
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digital logic circuit
This is a mind map about digital logic circuits, including sequential logic circuits, digital-to-analog and analog-to-digital conversion, pulse signal generation and shaping, programmable logic devices, etc.
2021-09-01 21:10:05 に編集されました
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digital logic circuit
sequential logic circuit
Latches
Basic RS latch (reset set) (two cross-coupled NOR gates used)
Gated RS latch (C control signal, respectively and RS AND operation first)
Gated D latch (when C=1, Q(n 1)=D)
trigger
Definition: Use a special timing control signal of a clock to limit the change time of the state of a memory unit
master-slave flip-flop
Master-slave RS flip-flop
Form: Two identical gated RS latches are connected. The control signal is provided by the external clock signal CLK. They are mutually inverted. The master-slave latches are alternately gated.
Keep, set to zero, set to 1, disable (RS are all 1)
Master-slave D flip-flop: Two identical D latches are connected, the control signal is provided by the external CLK, and they are opposite to each other.
Master-slave JK flip-flop
It is composed of a master-slave D flip-flop and several gate circuits.
Hold, set to 0, set to 1, flip (JK are both 1)
master-slave flip-flop
Advantages: It solves the somersault (multiple changes of the excitation signal) and oscillation of the latch (when the control signal is valid, which is equivalent to two combination circuits forming a feedback system that is a mutual feedback network, and the system may be affected by transient characteristics. unstable and oscillating)
Disadvantages: Requires the input data to remain constant during data reception by the main latch to avoid any interference
edge trigger
The flip-flop can only receive data when the clock transitions (rising or falling edge) (strictly speaking, within a very short period of time before and after the transition)
Maintain blocking edge trigger
CMOS edge trigger
Pulse operating characteristics
Setup time: The input signal arrives a period of time (Tset) before the edge of the clock pulse arrives.
Hold time: After the clock pulse arrives, the input signal must remain unchanged for a period of time (Th)
Transmission delay time: the time required from the edge of the time pulse until the new state of the flip-flop is stably established
Maximum clock frequency, pulse width, power consumption
Application examples
Anti-chatter switch: Eliminates a series of pulsating vibrations generated when a mechanical switch is turned off or turned on.
Asynchronous pulse synchronization
Single pulse generator: A circuit that converts an input pulse of arbitrary width into a single pulse with a defined width
Analysis and design of sequential logic circuits
analyze
Synchronization: output equation--driving equation--state equation--state table--state diagram--logic function
Asynchronous: pulse type/potential type
Synchronous timing design: state diagram--simplification and removal of redundant states--binary coding--flip-flop--drive output--self-starting characteristic check (when the number of states of the sequential circuit is not equal to the exponent of 2, there will be redundancy in the sequential circuit Invalid state, once the circuit enters the invalid state, it can automatically return to a certain valid state after a limited number of clocks)
Finite State Machine
Moore type: The output is only related to the current state of the finite state machine and has nothing to do with the input signal at the current time.
Mealy type: The output is not only related to the state at the current moment, but also related to the input signal at the current moment.
adventure
Asynchronous sequential logic circuit: It is difficult to determine the order in which the excitation signal and the clock signal arrive at the same flip-flop.
Synchronous sequential logic circuit: The gate has limited load capacity. In fact, one clock signal is used to drive several gate circuits, and then these gate circuits drive several flip-flops. However, due to the transmission delay time of each gate different
Elimination: Use synchronous instead of asynchronous to extend the signal transmission delay
counter
Asynchronous counter
Asynchronous binary counter: Each flip-flop is connected as a T' flip-flop, and the flip-flops are connected in series. The output of the low-order flip-flop is used as the clock input of the high-order flip-flop. The maximum operating frequency is f=1/nTpf
Asynchronous decimal counter: Based on the asynchronous binary adder, a NAND gate is added. The inputs of the NAND gate are Q3 and Q1. When both are 1, the NAND gate outputs low level and all flip-flops in the counter are cleared.
sync counter
Synchronous binary counter: composed of T flip-flop, T0=1; Ti=Q(i-1)Q(i-2)....Q1Q0; maximum frequency f=1/(Tpf Tpg)
Synchronized decimal counter
Reversible counter: can be added or subtracted
Universal sync integration
74163 (binary), 74160 (BCD), 74190 (reversible)
Arbitrary base counter
Feedback reset method: using the binary code of the corresponding state to generate an asynchronous clear signal through a combinational circuit
Feedback setting method (number setting): repeatedly placing a certain value into the counter to jump M-N states
application
Sequence signal generator: counter plus data selector
Keyboard scanning circuit
register
Sequential logic components that temporarily store secondary digital numbers
One type is a register composed of multi-bit D flip-flops in parallel. The data is stored when the effective edge of the clock arrives. The other type is composed of D latches. The data is stored at a certain agreed level of the clock. .
Shift Register
One-way shift register: serial in-serial/parallel out one-way shift register; serial/parallel in-serial out one-way shift register
bidirectional shift register
application
Programmable crossover
serial adder
serial accumulator
Sequence signal generator
shift register counter
ring counter
twisted ring counter
Digital-to-analog and analog-to-digital conversion
D/A converter
Classification
Inverted T-shaped resistor network D/A converter: only R and 2R,
Resistor network D/A converter: less resistance, but a big difference
Technical Parameters
Resolution: The ability to resolve the minimum output voltage
Conversion error: fluctuation of the reference voltage, zero point drift of the operational amplifier, on-resistance and on-voltage drop of the analog switch, deviation of the resistor resistance in the resistor network, half of the minimum output voltage
Conversion speed: Setup time, the time from the sudden change of the input digital quantity until the output voltage enters the range of -0.5LSB from the steady-state value
Accuracy: Comparing the actual output with the ideal value, it is determined by differential nonlinearity-integral nonlinearity
linearity, monotonicity
A/D converter
Basic principles: sampling, holding, quantization, encoding
Classification
Successive approximation A/D converter
Double integrating A/D converter: converts the input analog voltage signal into a time width signal proportional to it, and then counts clock pulses of a fixed frequency within this time width. The counting result is proportional to the input analog voltage. Digital signal
Technical Parameters
Resolution: Number of binary digits output
Conversion Error: Multiple of Least Significant Bit
Conversion speed: the time required to complete an AD converter conversion
Generation and shaping of pulse signals
555 integrated timer---basic structure: resistor divider, voltage comparator, RS latch, transistor discharge and lighting
Schmitt trigger circuit
Output characteristics: There are two stable states (high and low levels, but the stable state needs to be maintained by the input signal level); it has hysteretic voltage transmission characteristics
Using 555 timer to construct a Schmitt trigger circuit
Waveform transformation, pulse shaping, pulse amplitude identification
monostable trigger circuit
Composition and working principle: steady state, temporary steady state, temporary steady state duration t=RC, automatically returns to stable state
Pulse shaping, pulse delay, pulse timing
multivibrator
The self-excited oscillator can automatically generate a rectangular wave generator with a certain frequency and a certain pulse width after the power is turned on without the need for an external trigger signal.
Two transient stable states
programmable logic device
Basic structure: AND or array structure, lookup table structure (LUT)
PAL: Programmable vs Array, Fixed or Array
GAL: Programmable vs Array, Fixed or Array
CPLD: Programmable AND-OR array, output logic macrocell
FPGA: LUT, basic structure: IOB (programmable input and output module) CLB (configurable logic module) ICR (interconnect resource) SRAM (static memory)
Semiconductor storage device
ROM
Fixed ROM: address decoder plus storage array, information is stored during manufacturing
Programmable ROM
One-Time Programmable ROM (PROM)
Optically erasable programmable ROM (EPROM): avalanche injection write, bulk erase under UV
Electrically Erasable Programmable ROM (EEPROM): word erase and word rewrite functions under high voltage, tunnel effect
FLASH Memory
RAM
Address decoder memory matrix read and write control circuit
Bipolar RAM
Field effect transistor RAM
SRAM
DRAM: cyclic charging
combinational logic circuit
adventure
static adventure
Definition: Before and after the input changes, the steady-state output should not change, but during the input change process, glitches appear.
Classification
Functional adventure
Definition: When multiple input quantities change, the variables change at different speeds
Elimination: The strobe pulse appears after the changes in the circuit caused by input changes have stabilized, so that a risk-free steady-state output is obtained.
logical adventure
Definition: There is only one change in the input variable, which excludes functional hazards and actually represents the delay of the gate.
Elimination: Modify the logic design and add redundant terms (including product terms of the remaining invariant variables) to the simplest output; gated output
dynamic adventure
Definition: Before and after the input changes, the steady-state output should change, but during the process of the input changes, the output will briefly repeat
Elimination: It is generally caused by static risk in the front stage of the circuit. Therefore, static risk can be eliminated. Dynamic risk can also be eliminated.
Verilog language--FPGA implementation of DDS
Encoder
binary encoder
Mutually exclusive encoder, at the same time, only one of the N input terminals of the encoder is at a valid level
priority encoder
8-wire-3-wire priority encoder 74148
10-wire-4-wire priority encoder 74147
Decoder/data distributor
Two-line and four-line decoder, three-line and eight-line decoder, four-line and 16-line decoder
display decoder
data selector
N data input terminals, k address code input terminals, and one data output terminal
arithmetic operation circuit
basic adder
Half adder HA: only considers the addition of two one-bit binary numbers, regardless of the carry of the low bit.
Full adder FA: taking into account the low carry, it can be implemented with two half adders and an OR gate
serial carry adder
high speed adder
Fully parallel adder: The multi-bit adder output sum S and the highest carry signal can always be written as the simplest logical expression of the input signals A and B. Therefore, a two-level gate structure can be used to realize the circuit logic function, but when the number of bits is too large , the number of gate circuits will increase sharply, and the circuit structure will be too complex.
carry-ahead
Idea: The carry input signal added to each full adder is obtained in advance through the logic circuit
Carry-ahead circuit CLA: The carry signal can be expressed as a function of P and G, G=AB; P=A B; when P and G are known, the carry signal can be obtained as long as it goes through the delay of the two-level gate circuit .
The carry-lookahead adder usually uses a 4-bit adder as a basic module and implements an adder with a multiple of 4 bits in a hierarchical structure.
full subtractor
Numeric comparator
transcoder
logic gate circuit
Switching characteristics of transistors: semiconductor diodes, transistors, MOS tubes
Discrete component gate circuits: diode AND gate, diode OR gate, transistor NOT gate
TTL gate circuit
Voltage transfer characteristics of TTL NAND gate
digital logic basics
coding
BCD code: 8421 code, 5421 code, 2421 code, remaining 3 codes
Gray code: cyclic code. There is only one difference between two adjacent codes, and the remaining bits are the same.
parity check code
Alphanumeric code: ASCII (7 bits)
Basic laws and rules of logical algebra
Basic rules: substitution, inversion, duality
Commonly used formulas, basic laws, exclusive or identical or logical operations
Standard form of logical function
Minimum term
Standard AND or formula
Maximum term
standard OR and
Simplification of logical functions
formula method
Karnaugh map simplification