Missing contact windows, parasitictransistors, oxide breakdown, etc.

Bulk defects (cracks, crystal imperfections),surface impurities, etc.

Contact degradation, seal leaks, etc

Dielectric breakdown, electromigration, etc.

Identifies target faults

Limits the scope of test generation

Makes analysis possible

Makes test effectiveness measurable byexperiments

Defect: An unintended difference between the implemented hardware and its intended design

Fault: A representation of a “defect” at abstracted functional level

Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states

Failure: Deviation of a circuit or system from its specified behavior

Single Stuck-At Faults

Multiple Stuck-At Faults

Bridging Faults (Input- Input/Output-Output)

Feedback Bridging Faults (Output-Input)

CMOS Transistor Stuck-On Faults

CMOS Transistor Stuck- Open Faults

Wire Break (Open) Faults

Common in memory cells of high density RAMs

Pattern-sensitive faults

Coupling fault

Gate delay fault model (a local delay fault model)

Path delay fault model (a global delay fault model)

sensitized path

be sensitized to the fault f by the test

exists a test t that detects f

for all input x zf (x)=z(x)

doesn't change the functionof circuit

prevent the detection of another fault

fault simulation

Complete detection test set

fault coverage

z(t)=z(t)forallt

No test can distinguish between fa and fb

Any test which detects one of them detects both faults

n+2 instead of 2n+2 faults

Collapsed ratio=final faults/original faults

every test (sequence) for α is also a test (sequence) for β

No test can distinguish between fa and fb

Any test which detects one of them detects both faults

For each n-input gate, we only need to consider n+1 faults

Primary-input

Fanout-Branches

A test set that detects all single stuck-at faults on all checkpoints of a combinational circuits also detects all single stuck-at faults in that circuit