1.Design definition
Solution verification, system design and FPGA chip selection
2. Code implementation
Express each divided functional module in a hardware description language. Commonly used hardware description languages include Verilog HDL and VHDL.
3. Functional simulation
Functional simulation is to verify the logic function of the circuit designed by the user before compilation. The simulation at this time has no delay information and only detects the preliminary functions.
4. Logical synthesis
Convert high-level abstraction language descriptions into lower-level circuit structures
5. Pre-simulation
Pre-simulation is also called post-synthesis simulation. During simulation, the standard delay file generated by synthesis is back-annotated into the comprehensive simulation model.
6. Placement and routing
①Layout
The layout process is the process of "placing" each gate in the gate-level netlist into the CLB. This process is a mapping process.
②Wiring
Wiring is the process of using the rich wiring resources in FPGA to connect CLBs together according to logical relationships.
static analysis
The method of static timing analysis is to find the longest path delay between registers and registers in the actual circuit after layout and routing. The maximum clock rate of the system can be obtained through the maximum delay. Static timing analysis is also automatically completed by EDA tools, and delay path information can be analyzed in the generated timing report.
7. Post-simulation
Post-simulation, also called timing simulation, back-notes the delay information of placement and routing into the design netlist to detect whether there are timing violations.
8.Board level debugging
Download the data file (bit data stream file) generated by the EDA software to the FPGA chip for actual testing.
After layout and routing, the connection length between gates is also determined, so the post-simulation contains the most complete and accurate delay information, which can better reflect the actual working conditions of the chip.
The gate-level netlist generated after synthesis only represents the virtual connection relationship between gates, and does not specify the location and connection length of each gate. Placement and routing is a process of determining the location and wiring information of the gates in the gate-level netlist.
Placement and routing is sometimes called implementation and placement and routing. Placement and routing configures the gate-level connection relationships in the logical netlist to the inherent hardware structure inside the FPGA chip. The place-and-route process physically configures each gate into a fixed-position programmable logic block (CLB)
Synthesis is a creative transformation process. It can not only translate our circuits, but also optimize our circuits, such as removing redundant circuit structures in circuit descriptions, or reusing circuit structures with the same function.
Convert the circuit logic described in the hardware description language into the interconnection relationship of basic logic units such as AND gates, OR gates, NOT gates, and flip-flops, which is what we often call a gate-level netlist.
Device delay and path delay.
Device delay is the delay time when the signal is transmitted through the device, and the device delay is related to the characteristics of the device itself; path delay is the delay time when the signal passes through the connecting line, which is proportional to the length of the connecting line.
Commonly used code editor software includes notepad and UltraEdit. They support highlighting, code completion, custom shortcut keys and other functions of almost all mainstream programming languages. They have beautiful appearance, powerful functions, strong scalability, and rich plug-in packages. , greatly improve work efficiency
According to the task requirements, evaluate the indicators and complexity of the system, weigh the working speed and the resources and cost of the chip itself, and select a reasonable design solution and appropriate device type.
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