Check map file

Adjust vector tables in .s files

nvic_vector_table_set(NVIC_VECTTAB_RAM, 0x00)

SystemInit();

Interrupt priority management

Interrupt vector table

Break nesting

Interrupt enable and disable

ISER (Interrupt Set-Enable Register): used to enable interrupts.

ICER (Interrupt Clear-Enable Register): used to disable interrupts.

ISPR (Interrupt Set-Pending Register): used to set interrupts to pending status.

ICPR (Interrupt Clear-Pending Register): used to clear the pending status of interrupts.

IPR (Interrupt Priority Register): used to set the priority of interrupts.

Usually used to implement the operating system's clock tick or simple delay function

Auto-reload: SysTick can be configured to automatically reload a preset value when the counter decrements to zero, thus enabling periodic interrupts.

Interrupt generation: When the SysTick counter decrements to zero, a SysTick interrupt can be triggered. This interrupt is usually used for task scheduling or time slice rotation of the operating system.

Simple and easy to use: SysTick is very simple to configure and use, usually only needing to set a few registers.

CTRL (Control and Status Register): used to control the working mode and status of SysTick.

LOAD (Reload Value Register): used to set the reload value of the SysTick counter.

VAL (Current Value Register): used to read the value of the current SysTick counter.

CALIB (Calibration Value Register): used to provide calibration information, usually used for the clock beat of the operating system.

Application scenarios

synchronous mode

asynchronous mode

Application scenarios

asynchronous mode

1. Prepare

2. Copy the FreeRTOS Kernel code file to the corresponding directory of the project

3. Modify code

4. Configure Keil project

5. Program reference FreeRTOS API

Reference header file

Directly modify the file name uproj -> uprojx

The NVIC supports up to 256 interrupt priority levels, but the GD32F307C typically only uses 16 of them. Each interrupt can be assigned a priority level, with lower priority values ​​indicating higher priority.

The NVIC uses an interrupt vector table to store the addresses of interrupt service routines (ISRs). When an interrupt occurs, NVIC will obtain the corresponding ISR address from the vector table based on the interrupt number, and jump to this address to execute the ISR.

NVIC supports interrupt nesting, that is, high-priority interrupts can interrupt low-priority interrupt processing.

The NVIC allows the enable and disable status of each interrupt to be controlled through registers.

Suitable for situations where synchronous and asynchronous communication are required, such as clock-synchronized data transmission with external devices.

Similar to UART

Simple point-to-point asynchronous communication, such as communicating with sensors, debugging tools, etc.

Only supports asynchronous communication mode