1) Concept, Requirements, and Planning
Product goals
Target market (mobile, data center, automotive, IoT)
Performance targets (frequency, throughput, latency)
Power targets (TDP, battery life, energy per operation)
Cost targets (die cost, package cost, test cost)
Reliability targets (lifetime, failure rate, safety standards)
Technology selection
Process node (e.g., 28nm, 7nm, 3nm; FinFET/GAA)
Foundry choice (PDK availability, yield maturity, capacity)
IP strategy (in-house vs licensed)
Schedule and risk management
Tapeout timeline and milestones
Long-lead items (masks, substrates, tools, capacity)
Risk areas (new node, new IP, packaging complexity)
2) Chip Architecture and Microarchitecture
System definition
Compute blocks (CPU/GPU/AI accelerators/DSP)
Memory hierarchy (SRAM, cache levels, controllers)
Interconnect (NoC, buses, coherency)
I/O (PCIe, DDR, USB, Ethernet, SerDes)
Security (root of trust, secure boot, crypto engines)
Performance/power/area (PPA) trade-offs
Parallelism vs frequency scaling
Power gating, clock gating, DVFS
Cache sizing and bandwidth planning
Modeling and estimation
Area and timing budgeting
3) RTL Design and IP Integration
RTL coding
Languages (SystemVerilog/VHDL)
Synchronous design practices
Reset and clock-domain considerations
IP blocks
CPU cores, PHYs, memory macros, PLLs
Interface controllers and standardized protocols
Hard IP vs soft IP integration constraints
Power intent specification
Isolation, retention, level shifting strategies
DFT (Design for Test) planning
BIST for memories (MBIST)
Logic BIST where applicable
Boundary scan (JTAG/IEEE 1149.x)
4) Functional Verification
Verification methodologies
Constrained-random testing
Coverage-driven verification (functional + code coverage)
Formal verification
Equivalence checking between RTL and netlists
Emulation and prototyping
FPGA prototypes for software bring-up
Hardware emulation for large-scale validation
Software/firmware co-verification
5) Logic Synthesis and Timing Closure
Synthesis
RTL → gate-level netlist using standard cells
Constraints (SDC): clocks, IO delays, false paths, multicycle paths
Area/timing/power optimization passes
Static Timing Analysis (STA)
Setup/hold closure across corners (PVT: process/voltage/temperature)
Clock uncertainty, skew, jitter modeling
On-chip variation and derates
Power analysis
Dynamic (switching) vs leakage
Activity generation (SAIF/VCD) and estimation
6) Physical Design (Place & Route)
Floorplanning
Die size estimation and aspect ratio
Macro placement (SRAMs, analog blocks, PHYs)
Power grid planning (IR drop targets)
IO ring planning (for certain package styles)
Placement
Standard cell placement optimization
Congestion analysis and mitigation
Clock Tree Synthesis (CTS)
Skew minimization and insertion delay control
Clock gating placement and verification
Routing
Global routing and detailed routing
Shielding and spacing for critical nets
Antenna effects and fixes
Parasitic extraction
RC extraction and back-annotation
Post-route STA and SI (signal integrity) checks
Physical verification
LVS (Layout vs Schematic)
ERC (Electrical Rule Check)
Density/fill insertion (CMP uniformity)
Signoff analyses
EM/IR (electromigration/voltage drop)
Crosstalk and noise analysis
Reliability checks (BTI, HCI models as applicable)
7) Tapeout Preparation
Final signoff package
Verified GDSII/OASIS layout database
Timing, power, and physical signoff reports
Mask data preparation (MDP)
Fracturing for mask writers
OPC (Optical Proximity Correction)
RET (Resolution Enhancement Techniques)
Mask rule checks and data integrity validation
Documentation and release
Revision control, ECO finalization
Foundry deliverables checklist
8) Photomask (Reticle) Fabrication
Mask blanks and patterning
Chrome deposition and resist coating
E-beam or laser writing of patterns
Mask processing and inspection
Develop/etch processes for mask features
Defect inspection and repair
Pellicle mounting (when used)
Mask qualification
Critical dimension (CD) verification
Registration/alignment accuracy checks
9) Wafer Fabrication Overview (Front-End-of-Line to Back-End-of-Line)
Starting substrate
High-purity silicon ingot growth (Czochralski/Float-zone)
Wafer slicing, lapping, polishing (prime wafers)
Cleaning and surface preparation
Cleanroom manufacturing basics
Contamination control (particles, metals, organics)
Tool sets (litho, deposition, etch, implant, CMP)
Statistical process control (SPC) and metrology loops
10) FEOL: Transistor Formation
Isolation
Shallow Trench Isolation (STI) formation
Oxide fill and CMP planarization
Well and channel engineering
Ion implantation for wells (n-well/p-well)
Annealing (RTA/laser anneal) for dopant activation
Gate stack formation
Gate dielectric formation (SiO₂/high-k materials)
Gate electrode deposition (polysilicon/metal gate)
Patterning via lithography + etch
Source/Drain formation
Spacer deposition and etch
Extension implants and deep implants
Advanced device structures (as applicable)
FinFET fin patterning and formation
GAA nanosheet/nanowire stack formation
Strain engineering (SiGe, stress liners)
FEOL metrology and inspection
Electrical test structures (s-param, IV, etc.)
11) Lithography: Pattern Transfer Core Steps
Photoresist processing
Spin coat, soft bake, anti-reflect coatings
Alignment and exposure
DUV (193nm) vs EUV (13.5nm) choices
Overlay control across layers
Pattern enhancement and multi-patterning (when needed)
Double/quadruple patterning
EUV stochastic defect considerations
Etch pattern transfer
Etch selectivity and profile control
12) Deposition Processes
Dielectric deposition
CVD/PECVD for oxides/nitrides
ALD for conformal ultra-thin films
Metal deposition
PVD (sputter) seed layers
CVD/ALD for barrier/liner layers
Electroplating for copper fill
Epitaxy
Selective epi for stressors and junction engineering
13) Etch and Clean
Etch types
Plasma etch chemistries by material
Wet processing
Wet etch (HF, etc.) for selective removal
RCA cleans and megasonic cleaning
Post-etch residue control
Ashing and solvent cleans
Surface conditioning steps
14) Ion Implantation and Thermal Processing
Implantation
Dopant species selection (B, P, As, etc.)
Tilt/rotation for uniformity
Annealing
Rapid Thermal Anneal (RTA)
Spike anneal/laser anneal for shallow junctions
Diffusion control and defect healing
15) CMP (Chemical Mechanical Planarization)
Purpose and importance
Planar surfaces for lithography depth-of-focus
Removing overburden after deposition/fill
CMP steps
Slurry selection and pad conditioning
Challenges
Pattern density dependence and dummy fill
16) BEOL: Interconnect (Wiring) Formation
Dielectric stack
Interlayer dielectrics (low-k/ultra low-k)
Etch-stop and barrier layers
Via and trench patterning
Dual-damascene processes (for copper)
Lithography + etch to form features
Barrier/liner and metal fill
Ta/TaN, Co/Ru options in advanced nodes
Copper seed + electrofill
Alternative metals and air-gaps (advanced)
CMP to define metal lines
Removing overfill and planarizing
Multi-layer repetition
Local interconnect → intermediate → global layers
Wider/thicker top metals for power distribution
BEOL reliability
Via resistance and stress migration
TDDB (time-dependent dielectric breakdown)
17) Wafer-Level Metrology, Inspection, and Process Control
Critical dimension and overlay
Overlay metrology to control alignment
Defect inspection
Optical and e-beam inspection
Defect classification and pareto analysis
Electrical parametric testing (PCM)
Transistor Vt, leakage, resistance/capacitance monitors
Process drift detection and correction
Yield learning
Inline data analysis and feedback to tools
Root cause analysis and corrective actions
18) Wafer Sort (Probe) and Initial Electrical Test
Wafer probing
Probe cards contacting pads/bumps
Test patterns and speed grading
Test coverage goals
Scan tests, memory BIST, analog checks
Redundancy repair for memories (laser/e-fuse repair flows)
Binning
Sorting dies by performance/leakage
Marking/recording good dies (inkless mapping)
19) Assembly: Dicing and Packaging
Wafer backgrind and thinning
Thickness targets for package and thermal needs
Stress relief and handling considerations
Dicing (singulation)
Saw dicing vs laser dicing
Die edge quality and crack prevention
Die attach and interconnect
Wire bonding (legacy/low-cost)
Flip-chip bumping (C4, micro-bumps)
TSVs and 2.5D/3D integration (interposers, chiplets)
Substrate and package types
Leadframe packages (QFN, etc.)
Organic substrates (BGA, FC-BGA)
Silicon interposers for high-density routing
Underfill and encapsulation
Mechanical support and reliability
Moisture sensitivity management
Thermal solutions
Heat spreaders, TIM, lids
Thermal interface and junction temperature control
20) Final Test and System-Level Validation
Package-level electrical testing
Functional tests at speed (ATE)
Power, leakage, and IO compliance checks
Calibration and trimming (for analog/RF)
Burn-in and stress testing (as required)
Screening for early failures
System-level test (SLT)
Running real workloads to catch corner-case defects
Thermal and power stress scenarios
Quality metrics
Outgoing quality audits and sampling plans
21) Reliability Qualification and Compliance
Reliability standards and tests
HTOL, HAST/THB, temperature cycling
ESD and latch-up qualification
Mechanical shock and vibration (automotive/industrial)
Failure analysis (FA)
Optical inspection, SEM/FIB cross-sections
Emission microscopy and fault localization
Root cause and corrective action (RCCA)
Documentation and certification
JEDEC qualification reports
Automotive (AEC-Q) requirements when applicable
22) Production Ramp, Yield Improvement, and Cost Optimization
Yield ramp
Learning cycles from early lots
Defect density reduction and process tuning
Design/process co-optimization
DFM (Design for Manufacturability) improvements
Library/IP updates and ECOs
Cost reduction levers
Test time reduction and smarter binning
Package simplification where possible
Supply chain planning
Foundry capacity, OSAT scheduling
Materials procurement (substrates, gases, chemicals)
23) Shipping, Traceability, and Lifecycle Support
Logistics and traceability
Lot tracking from wafer to package
Serialization and anti-counterfeit measures
Field returns and continuous improvement
RMA handling and FA feedback loop
Firmware updates and errata management
Product lifecycle
Process changes and re-qualification
End-of-life planning and last-time buys
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