MindMap Gallery Combinational logic circuit module design
Digital logic and computer architecture, Chapter 3 of final review notes. Digital circuits can be divided into two categories based on different characteristics of logic functions. One type is called combinational logic circuits (referred to as combinational circuits), and the other type is called sequential logic circuits.
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Modular design
Language basics
Operation
zero extension
Unsigned number: the high bits with few digits are filled with 0 and the high bits with more digits are calculated.
Signed numbers: The high-order complement sign bit with a small number of digits is extended to the number operation with a large number of digits.
Reduction operation (unary reduction)
Includes & | ^ and ~^
The result is only one 1 or 0
For example: y=[4:0]a &a==y[0]&y[1]&y[2]&y[3]&y[4]
Shift operation
unsigned number
Logical shift left<<
Fill low bit with 0
Logical right shift >>
Fill the high bit with 0
signed number
Arithmetic shift left<<<
Fill low bit with 0
Arithmetic right shift >>>
High-order complement sign bit
The result of the operation is a logical value 1 0
Equality operation
==and!=
relational operations
< > >= and <=
There is an unsigned number in the expression (eg: 4'd5), and the others become unsigned numbers.
logic operation
!(monocular operation)&&(binary) and‖(binary))
Conditional operation?:
For example: assign y=s?d0:d1 s input is 1, the result is d0, otherwise it is d1
Bit-mixed operations (bit-splicing operations)
Y={B[0],2C[1],2b′10} constant bit width cannot be omitted
Copy operation {n{A}}, splice signal A repeatedly n times
type of data
variable
logic [7:0] a eight-bit unsigned vector signal
Polymorphism
Single source drive signal
output logic a
Line network (multiple inputs)
tri [7:0] a eight-bit tri type vector signal
Multi-source driving signals
output tri a
Modeling method
Behavioral modeling (direct modeling through causal relationships between inputs and outputs)
assign (continuous assignment)
assign #5 out = A&B; //Assign the value to out after a delay of 5 time units. #5 is used for simulation and cannot be synthesized.
assign out=A&B; Once a quantity changes on the right side, the value on the left side is immediately reassigned
The left side can be logic or tri; any input changes will immediately affect the output results.
always and initial (based on procedure blocks)
Blocking assignment out=a&b . The previous statement is not completed and the following statement cannot be executed.
Grammar
initial is used for simulation. always can be used for modeling and simulation, similar to an infinite loop.
No assignment. The left side must be a variable (such as logic) and cannot be wired.
begin...end (equivalent to {})
always_comb begin … end endmoudle
branch structure
if…else
begin end flag range
case
case endcase flag range
casez
Conditional judgment can be added?, this bit is always true
Loop structure
for
begin end is equivalent to braces!
repeat
reapeat (specify the number of loops) statement block;
while
forever
(infinite loop) forever statement block
Structured modeling (divide complex circuits into multiple sub-modules, then model and combine them separately)
Structured modeling
Module instantiation
Gate level modeling
Parametric modeling (parameter declares parameters, similar to macro definition)
usage
generate statement
generate…endgenerate
test program
elements
excitation
Module to be tested
Output
Signal
Module to be tested
response
structure
Signal definition Module instantiation Add stimulus show output results
Example
stimulus signal
Initial process block, linear excitation
always process block, loop stimulus
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