MindMap Gallery Fundamentals of digital electronics technology (flip-flops)
"A Concise Tutorial on the Basics of Digital Electronic Technology" Tsinghua University. Yu Mengchang. Fourth Edition (Chapter 5 Triggers), with detailed introduction and comprehensive description, I hope it can help interested friends learn.
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This is a mind map about plant asexual reproduction, and its main contents include: concept, spore reproduction, vegetative reproduction, tissue culture, and buds. The summary is comprehensive and meticulous, suitable as review materials.
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Digital Electronics Technology Basics
Chapter 5 Trigger
Overview
Basic requirements for triggers
①Has two stable states that can maintain themselves - 0 state and 1 state
② Able to receive, save and output signals, that is, when a trigger signal is applied, the output state of the circuit can be flipped; after the trigger signal disappears, the new state obtained can be saved
The current and secondary states of triggers
Classification of triggers
Basic flip-flop: input signal is applied directly to the input terminal
Synchronous flip-flop: The input signal is input through the control gate, and the control gate is controlled by the clock pulse CP signal. The input signal can only be received when the CP signal arrives.
Edge trigger: The input signal can only be received at the rising edge or falling edge of the CP signal
5.1 Basic triggers
Definition of status:
Basic flip-flop composed of NAND gate
Circuits and symbols
Logic circuit diagram:
Logical symbols:
Notice
The characteristic table and characteristic equations of the basic flip-flop composed of NAND gates are the same as those of the basic flip-flop composed of NOR gates.
Basic flip-flop composed of NOR gate
Circuits and symbols
Logic circuit diagram:
Logical symbols:
symbolic representation
R is called the set-0 input terminal, which is customarily called the reset terminal.
S is called the set 1 input terminal, which is customarily called the set terminal.
Characteristics table:
The status is uncertain when the signals of R=S=1 are canceled at the same time.
Characteristic equation:
Integrated basic triggers
CMOS integrated basic flip-flop
TTL integrated basic trigger
Characteristics of basic RS flip-flops
advantage
Simple structure
Has the functions of setting 0, setting 1 and holding
shortcoming
Poor circuit anti-interference ability
There are constraints between R and S, that is, the two inputs cannot be high level at the same time.
5.2 Synchronous triggers
Synchronous RS flip-flop
Logic circuit diagram:
National standard symbol:
Characteristics table:
Characteristic equation:
There are constraints between RS
During CP=1, if R=S=1, there will be an abnormal situation in which Q and Q are not both 1.
During CP=1, if R and S are canceled in time, set to 0 or set to 1, and the status is determined.
During CP=1, if R and S jump from 1 to 0 at the same time, a race condition will occur and the result will be uncertain.
If R=S=1, CP is suddenly withdrawn, that is, CP jumps from 1 to 0, a race condition will also occur, and the result is uncertain.
Synchronous D flip-flop
Logic circuit diagram:
Characteristic equation:
Features
Unconstrained problem
During CP=1, the output terminal changes with the input terminal.
When the falling edge of the CP pulse arrives, it is latched, and the stored content is the value of D at the moment of the falling edge.
Integrated synchronous D flip-flop
TTL integrated synchronous D flip-flop
CMOS integrated synchronous D flip-flop
5.3 Edge trigger
Edge D flip-flop
National standard symbol:
Characteristic equation:
Features of edge D flip-flop
CP edge (rising or falling edge) trigger
Strong anti-interference ability
Only the function of setting 0 and setting 1
The role of the asynchronous input terminal
Synchronous input terminal: D is called the synchronous input terminal, because the input signal at D terminal is controlled by the clock CP
Asynchronous input:
Edge D flip-flop with asynchronous input:
Integrated edge D flip-flop
COMS edge D flip-flop CC4013
symbol:
Lead-out function:
Characteristics table:
TTL edge D flip-flop 7474
symbol:
Lead-out function:
Characteristics table:
Edge JK flip-flop
National standard symbol:
Characteristic equation:
Characteristics table:
Features of edge JK flip-flop
CP edge (rising or falling edge) trigger
Strong anti-interference ability
Complete functions, flexible and convenient to use
Integrated JK edge trigger
CMOS edge JK flip-flop CC4027
National standard symbol:
Lead-out function:
Characteristics table:
TTL edge JK flip-flop 74LS112
National standard symbol:
Lead-out function:
Characteristics table:
Function classification, function representation method and conversion of edge triggers
Edge trigger logic function classification
JK type flip-flop: Any circuit with the functions of holding, setting 1, setting 0 and flipping is called JK type flip-flop.
D-type flip-flop: Any circuit with the function of setting 1 and setting 0 is called a D-type flip-flop.
T-type flip-flop: Any circuit with hold and flip functions is called T-type flip-flop
symbol:
Characteristics table:
Characteristic equation:
T' type flip-flop: Any circuit that flips once every clock pulse is called a T' type flip-flop.
symbol:
Characteristics table:
Characteristic equation:
Edge trigger logic function representation method
Property table (truth table)
D flip-flop:
JK trigger:
kanotu
D flip-flop:
JK trigger:
Characteristic equation
State diagram
D flip-flop:
JK trigger:
Timing diagram
D flip-flop:
JK trigger:
Edge trigger logic functions represent transitions between methods