1) Product Definition & Requirements
Target applications (mobile, automotive, AI, IoT, etc.)
Key specs
Performance (frequency, throughput, latency)
Power (TDP, energy per operation)
Reliability/lifetime requirements
Environmental/qualification standards (AEC-Q, etc.)
Technology choices
Process node (e.g., 180nm → 3nm class)
Device architecture (planar CMOS, FinFET, GAAFET)
Packaging level (wirebond, flip-chip, 2.5D, 3D)
Supply chain & manufacturing strategy
IP and EDA tool selection
2) Architecture & Microarchitecture
System architecture
CPU/GPU/NPU selection or custom accelerators
Memory hierarchy (SRAM, cache levels, DRAM interface)
Interconnect (NoC, buses, coherency)
Security architecture (secure boot, encryption engines, key storage)
Microarchitecture design
Pipelines, execution units, vector/Tensor units
Clocking and power domains
Debug/trace features (JTAG, trace macrocells)
Modeling & feasibility
Performance modeling and workload simulation
Power/performance tradeoff exploration
3) RTL Design & IP Integration
RTL coding (Verilog/SystemVerilog/VHDL)
IP blocks
Analog/mixed-signal IP (PLL, ADC/DAC, PHYs)
Interface IP (PCIe, USB, DDR, Ethernet, MIPI)
Third-party cores (CPU, GPU)
Design for test (DFT) planning
Scan chains, boundary scan (JTAG)
Built-in self-test (BIST) for memories/logic
Test points and compression
Low-power design methods
Power gating with retention
DVFS (dynamic voltage/frequency scaling)
4) Functional Verification
Verification strategy
Testbench architecture (UVM)
Coverage targets (code/functional/assertion)
Simulation & formal
RTL simulation (directed + constrained-random)
Formal verification (property checking)
Equivalence checking (later vs RTL)
Emulation & prototyping
FPGA prototyping for early software bring-up
Hardware emulation for large designs
Bug tracking and regression infrastructure
5) Logic Synthesis & Netlist Generation
Constraints definition
Timing (SDC), clocks, IO delays
Multi-mode, multi-corner (MMMC)
Synthesis
Optimization (retiming, logic restructuring)
Technology mapping to standard cells
Pre-layout checks
Linting and CDC/RDC (clock/reset domain crossing)
Early static timing analysis (STA)
6) Physical Design (Place & Route)
Floorplanning
Die size estimation and utilization
Macro placement (SRAMs, PHYs)
Power grid planning (rings/straps/mesh)
IO/pad placement (if applicable)
Placement
Congestion analysis and optimization
Clock Tree Synthesis (CTS)
Clock distribution topology
Clock gating cell insertion
Routing
Global routing → detailed routing
Shielding and critical net routing
Antenna effect mitigation
Signoff analysis
Timing closure (setup/hold across corners)
Power analysis (dynamic + leakage)
IR drop and electromigration (EM) checks
Signal integrity (crosstalk, noise)
Physical verification (DRC/LVS)
7) Design Signoff & Tape-Out
Final signoff deliverables
GDSII/OASIS (layout database)
Timing models (SDF), parasitics (SPEF)
Test patterns (ATE vectors)
Documentation and manufacturing notes
Mask data preparation
OPC (optical proximity correction)
Fracturing (layout → mask writer format)
Tape-out milestone
Release to foundry/mask house
8) Wafer Fabrication (Front-End-of-Line: FEOL)
Starting material
Silicon ingots (Czochralski) and wafer slicing
Wafer polishing (CMP) and cleaning
Wafer types (p-type/n-type, orientation, SOI)
Core repeating process steps (cycle across many layers)
Thin film deposition
CVD/PVD/ALD for dielectrics and metals
Epitaxy for high-quality silicon layers
Photolithography
Photoresist coating (spin coat)
Mask alignment and exposure (DUV/EUV)
Post-exposure bake and development
Etching
Wet etch vs dry plasma etch (RIE)
Pattern transfer into films
Doping
Ion implantation (dose/energy control)
Diffusion/anneal (activate dopants, repair damage)
Planarization
Chemical mechanical polishing (CMP)
Cleaning & contamination control
Ultra-pure chemicals, DI water rinses
Particle control in cleanrooms
Transistor formation (high-level)
Well formation (n-well/p-well)
Isolation (STI: shallow trench isolation)
Gate stack creation
High-k dielectrics and metal gate (HKMG)
Gate patterning and critical dimension control
Source/drain engineering
Silicidation for lower resistance
Advanced nodes specifics (conceptual)
FinFET/GAAFET channel formation
Multi-patterning (if needed)
9) Wafer Fabrication (Back-End-of-Line: BEOL)
Interconnect stack build-up
Interlayer dielectrics (low-k materials)
Via and trench patterning (dual damascene for copper)
Metal deposition and fill
Copper electroplating or alternative metals (e.g., cobalt, ruthenium)
CMP to planarize each metal layer
Multi-level routing
Lower metals for local interconnect
Upper metals for global power/clock routing
Passivation
Protective top coatings (SiN/SiO₂)
10) In-Line Metrology & Process Control
Critical measurements
CD-SEM (critical dimension)
Overlay accuracy (layer alignment)
Film thickness/refractive index (ellipsometry)
Defect inspection (optical/e-beam)
Electrical process monitoring
Test structures (scribeline)
Sheet resistance and contact resistance
Statistical process control (SPC)
Yield learning and drift correction
Tool calibration and maintenance
11) Wafer Probe / Sort (Electrical Testing on Wafer)
Wafer probing
Probe cards contact pads/bumps
Parametric tests and functional tests
Bin sorting
Speed binning (frequency/voltage corners)
Identifying defective dies
Yield analysis
Failure mode classification
Feedback to fab for process improvements
12) Dicing, Die Attach, and Packaging (Assembly)
Wafer backgrind/thinning (if required)
Improve package height, thermal characteristics
Die attach and interconnect
Wire bonding (cost-effective)
Flip-chip bumping (higher performance, better IO density)
TSV/3D stacking (advanced)
Substrate and package types
Fan-out wafer-level packaging (FOWLP)
2.5D interposer (HBM, chiplets)
Chiplet-based multi-die packages
Encapsulation and lid/heat spreader
Mold compound, lid attach
Thermal interface materials (TIM)
13) Final Test, Burn-In, and Quality Screening
Automated test equipment (ATE)
Functional patterns, scan testing, BIST
Power and leakage measurements
Stress testing
Burn-in to screen early-life failures
HTOL (high-temp operating life), HAST, temperature cycling
Reliability and qualification
Automotive/industrial qualification flows (if needed)
14) System Bring-Up & Validation
Silicon bring-up
Power sequencing, clocking, reset validation
Firmware boot and debug interfaces
Software enablement
Drivers, OS support, compilers/toolchains
Issue resolution and respins
ECOs (engineering change orders)
New mask revisions if required
15) Yield Ramp, Volume Production, and Lifecycle
Ramp to high-volume manufacturing (HVM)
Process tuning to increase yield
Cost optimization
Die size reductions, packaging alternatives
Test time reduction and improved binning strategy
Continuous monitoring
Field returns analysis (RMA)
Long-term reliability tracking
End-of-life planning
Last-time-buy, product discontinuation strategy
Key Enablers Across the Whole Flow
Cleanroom infrastructure
ISO class control, filtration, gowning protocols
Vibration/temperature/humidity control
Materials and chemicals
Ultra-high-purity gases and chemicals
Photoresists, developers, etchants, slurries
Tooling ecosystem
Lithography scanners (DUV/EUV)
Etchers, deposition tools, ion implanters, CMP tools
Metrology and inspection systems
Data and automation
Manufacturing execution systems (MES)
Traceability and lot genealogy
AI/ML for defect detection and yield learning
Security and IP protection
Secure data transfer and mask handling
Anti-counterfeit measures in packaging and supply chain
Wondershare EdrawMind
